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shindengen electric mfg.co.,ltd - 1 - confidential mcz 5203 se application note mar , 201 2 ver1.0
shindengen electric mfg.co.,ltd - 2 - confidential cautions for use thank you for purchasing our products . this manual contains important information on the safe use of our products . your safety is of the utmost importance to us. please read these instructions carefully before using our products . the following symbols mean: ! warning improper use of the products can result in death, serious injury, or expensive damage to equipment. ! caution improper use of the products can result in minor injuries or damage to equipment. ! ! warning warning although we are constantly making every effort to improve the quality and reliability of our products, there nevertheless remains a certain probability that the semiconductor products may occasionally fail or malfunction. please take careful precautions against product failures or malfunctions to avoid any injuries, fire accidents or social loss by implementing safety designs such as redundancy designs, designs for fire spread prevention, and designs for preventing malfunctions. our semiconductor products listed in this document are not designed or ma nufactured to be used in device s or systems requiring extremely high levels of quality and reliability, or the failure or malfunction of which may directly threaten human lives or cause injury. i n the cases where the products are to be used in device s or s ystems for special applications or devices or systems for specialized applications shown below, always make sure to consult us in advance. special applications transportation device s (automotive, marine, etc.), communication devices for core network , t raffic signal devices, fire prevention/anticrime devices, various safety devices, medical devices, etc. specialized applications nuclear power control systems, aircraft and aerospace devices, submarine relay devices, and systems for preserving life, etc. even if it is not for a special or specialized application, when ic products are to be used for devices or systems that are desired to last for a long period under continuous operation, please make sure to consult us in advance. ! ! ! ! ! cautio n cautio n cautio n cautio n cautio n do not attempt under any conditions to repair or mod ify ic products by yourself. doing so could result in electric shock, device breakage, fire, and malfunction . when an abnormal condition occurs, an excessive voltage or under voltage may be generate d across the output terminals of the circuit. install pre ven ta tive measures (e.g. over - voltage protection, over - current protection) for the device by considering the possibility of a malfunction and/or breakage of a load in an abnormal condition. do not switch on the circuit before confirming the proper connec tion and polarity of input and output terminals as an erroneous connection may cause breakage of the protection device or smoke/fire. do not use the circuit beyond the rated input voltage and install a protection device on the input rail to prevent smoke /fire that may be caused from an abnormal condition. if a breakdown or other abnormal condition occurs during the use of the device, immediately stop power to the device and consult us at your earliest possible convenience. we reserve the right to make any changes to the contents of this manual without prior notice in accordance with modifications to ic products . details of specifications should be exchanged at the adoption of the ic products . all information include d in this manual is believed to be accurate and reliable. however, our company takes no responsibility for any injury or damage incurred when using the ic products as described in this manual. neither do we take any responsibility for issues arising from i nfringement of patent or other rights caused by using this manual. the provision of this manual do es not guarantee the right to use any third party? s patent or other rights , or grant permission to use the patent or other rights of our company. no part of this manual may be reproduced or copied without the specific written consent of shindengen electric mfg. co., ltd. we are happy to provide circuit design support for safe use of the ic. please consult our sales representative . mcz5203 se standard power supply
shindengen electric mfg.co.,ltd - 3 - confidential index 1 : general description 1. 1: features 4 1. 2: block diagram ( sop22 ) 4 1. 3: pin assignment 5 1. 4: functions 5 1. 5 : application circuits 6 2 : symmetric llc converter operating description 2.1 : features 7 2.2 : f u ndamental circuitry 7 2.3 : operating waveform example 7 2.4 : control characteristics 8 2.5 : major p arameters and components 8 2.6 : ic operation 9 - 10 3 : selecting peripheral components 3.1: oscil l ator rt 1 1 3. 2: vsen se brown - out protection rvsensel 1 2 3. 3: soft start css 1 2 - 1 3 3. 4: ocp rocpdet/rocpl 1 3 - 1 4 3. 5: di/dt protection 1 4 3. 6: time r latch protect ion c timer 1 5 3. 7: high side floating vcc (vb) 1 6 3. 8: gate driver 1 6 4 : circuit diagram 4.1: t ypical circuit example 1 7 5 : dimensions 5 .1 : sop22 ( mcz5203 se ) 18
shindengen electric mfg.co.,ltd - 4 - confidential 1 general description mcz5203 is an advanced symmetri c llc current resonant mode controller for bridge converter . bulit - in high voltage direc t gate drivers, control circuit and optimized protections allow simplified and space /cost - saving design of power supplies for : ? large screen flat panel tvs (pdp / lcd ) psu ? laser printer psu ? high power adapters 1.1 features 1. r o bust 600v gate driver directly drives high side switch. 2. optimized gate drive capability minimizes the number of components for gate drive circuit . 3. o ptimized protective functions (ocp/burst/timer delayed latch/thermal) for llc converter 4. advanced zvs boundary chaser (capacitive mode prot ection) eliminates below resonant (capacitive di/dt) operation . 5. ocp operates by detecting peak primary current with 0.345v / threshold. 6. v cc supplies up to 35v with 13.5 v/8.4v uvlo 7. built - in voltage regulator of 10v for gate driver 8. independent high side / lo w side g ate driver uvlo with hysterisis 9. adjustable soft starting function 10. anti - di/dt startup function eliminates improper startup o f non zvs operation 11. optimized brown out protection 1.2 block diagram sop22
shindengen electric mfg.co.,ltd - 5 - confidential 1.3 pin assignmen t 1.4 functions p in number sop22 name function 1 vsen dc input voltage monitoring 2 fb f eedbac k signal input with f eedbac k loop open detection 3 ct timing capacitor ct determines dead time and fmin (minimum operating frequency) and also fss(startup frequency) 4 rt timing resistor rt determines fmin 5 gnd signal ground. t his pin should be connected to pgnd directly . 7 timer c timer determines the time period of burst mode in ocp or another abnormal operation . 8 ss s tart up timing capacitor css determines the soft - start ing time 10 vc1 voltage supply input for control circuit with 1 3. 5v/8.4v uvlo maximum rated voltage is 35v 12 ocp main resonant current sensing with +0.345v threshold for peak current limiting ,+/ - 60mv for didt protection 1 3 vc2 voltage regulator output for gate driver vc2=10v . 1 4 pgnd power ground this pin should be connected to low side mosfet source directly 1 5 vgl low side gate drive r output 6,9,11,16, 17,18,19 (nc) n o connection 20 vb v oltage source of high side gate driver supplied from vc2 through bootstrap circuit 21 vs floating driver reference voltage ( = source pin of high side mosfet) 22 vgh high side gate drive r output
shindengen electric mfg.co.,ltd - 6 - confidential 1.5 applicable circuits most simple sepp(single ended pu sh - pull) input ripple current reduction (half bridge) high power (full bridge)
shindengen electric mfg.co.,ltd - 7 - confidential 2 symmetric llc converter operating description 2.1 features symmetric llc res onant converter application is expanding widely due to its extreme ly high power conversion efficiency and low noise characteristics. it?s resonant tank consists of l/l/c connected in series . zvs/zcs operation minimizes switching loss and voltage spike. a) the voltage applied to main switch is clamped to input voltage (vbulk), consequently no spike voltage is generated. b) main switch turn - off current can be kept to constant and low level independent of load condition. c) transformer is excited symmetrically, thu s magnetics size can be minimized. d) sinusoidal resonant current waveform results in ex tremely low emi characteristics . e) output rectified current is also partially sinusoidal, and trr loss and switching noise can be minimized. f) the voltage applied to output diode is clamped to the output voltage (or x2) independent of load condition or input voltage . g) excellent cross regulation characteristics for multiple output converters due to symmetric bridge operation. h) no requirement of a uxiliary 3 rd winding helps to opt imi ze resonant condition and transformer design 2.2 fundamental circuitry sepp lr lm cr rl vbulk q 1 q 2 d 1 c p 1 d 2 c p 2 fig.1 llc configuration lr : 1 st resonant inductance lm : 2 nd resonant inductance (magnetizing inductance) cr :resonant capacitance cp1/2 :zvs res onant capacitance q1/q2 :main switch d1/d2 :commutating diode rl : equivalent load resistance fig.2 simplified dc/dc converter 2.3 operating waveform example fig.3 vds / idrain / vo ripple fig.4 zoom of turn off period o utput ripple voltage(vo) q2 vds (v ds2 ) q2 idrain (id(2)
shindengen electric mfg.co.,ltd - 8 - confidential 2.4 control characteristics voltage vs.frequency characteristics are shown in fig.5. llc converter operates in above - resonance region. (above zvs boundary) output voltage c an be stabilized by varying operating frequency , decreasing the operating frequency when input voltage becomes lower or load becomes larger, and increasing when higher or smaller respectively. fig.5 output voltage vs operating frequency characteristics 2.5 major p arameters and components table 1. major parameters vc1 ic vcc supply 15 - 2 2 vdc is recommended.(min.14.0v for startup in worst case) vbulkreset brown ? out detection voltage threshold bro wn - out protection operating voltage. the threshold value is determined considering resonant condition and hold - up time. fmin m inimum frequency f min is determined considering resonant frequency at vin min / po max condition . fmax m aximum frequency f max i s determined considering controllable area at vbulk max with min load and zvs condition. fss startup frequency f ss is determined considering mosfet vds,output diode inrush current and vout rise timing during startup tss s oft start ing time required soft s tarting time t timer b urst mode operation interval especially important for short circuit condition and feedback loop open condition . see section 3. 6 table 2 . recommended component s rvsenseh vbulk divider high side isense =1ua required h igh voltage assu red type is recommended. ct t iming capacitor ct determines fmin / fmax / fss / dt .s table temperature characteristics type is recommended. in case of mlcc, type ch or cog. rocph c urrent sensing filtering resistor primary current sensing filtering resisto r. around 10 ohm is recommended. cocpl c urrent sensing filtering capacitor primary current sensing filtering capacitor. 1000pf - 10000pf. rfb i(f/b) limitation resistor limiting i(f/b) and setting fmax . normally a few k ohm s. refer to characteristic diag rams. table 3 . circuit constants obtai ned from the formulas rvsensel vbulk divider low side obtained from vbulkreset and rvsenseh . rt timing resistor obtained from fmin and ct rocpdet s ensing resistor primary resonant current sensing rocpl ocp sensin g divider primary current sensing voltage divider css soft start timing capacitor obtained from tss. c timer burst ope ration timing capacitor obtained from t timer zvs boundary vout frequency
shindengen electric mfg.co.,ltd - 9 - confidential 2.6 ic operation power on mode a : under the condition of input bulk voltage vbulk is app lied ( vsense >1.4v ) , operation starts when vc1 terminal voltage reaches 1 3.5 v. a fter soft starting period ( tss ), the frequency is stabilized at nominal operating frequency depending on resonant tank and input/output condition. power on mode b : when vb ulk is applied after vc1 is supplied, gate drive pulse is generated at vsense > 1.1 v with fixed fss operation. then normal soft starting operation begins when vsense reaches 1. 4 v a nd operation is stabilized in normal operating frequency after the soft st arting period as mode a. power off mode a : under the condition of input bulk voltage vbulk is applied vsense >1.4v , ic operation stops when vc1 reaches the threshold of vc1 uvlo off 8.4v . power off mode b : when vbulk decreases under the condition of continuous vc1 supplied, o perating frequency decreases toward fmin. the frequency starts increas ing to fss level soon after vsense decreases to 1.4v. gate drive stops when vsense voltage decrease s to 0.7v. fig 6. power on / off timing diagram
shindengen electric mfg.co.,ltd - 10 - confidential under abnormal condition: a) feedback loop open: when operation is out of control due to input/output conditions beyond the controllable operating area,the frequency becomes to minimum ( fmin ). f/b loop open detector then will be activated and the gate output stops after the period of t timer set by timing capacitor ( c timer ). after the time period set by the burst mode( tb ), the output restarts and is latched off in the case where this timer - latch protection operating cycle repeats twice. restart vc1 to release latching. b) ocp / olp : when the voltage applied to ocp terminal exceeds vocp th (0.345v typ), the frequency increases instantaneously and when this condition is retained, the operation follows same as above. c) d i/dt timer ection : in close to below resonant c ondition, di/dt timer ection activates by detecting the threshold of vdidt (+/ - 60mv), limits the frequency to decrease and restrains the output voltage. see section 3.5 for detail. d) thermal timer ection : if ic i nternal temperature exceeds 140 c , output will be stopped with 40 c temperature hysteresis. remarks: w h en vbulk keeps low level , the converter is unable to stay in normal operation due to the f/b loop open timer ection and vsense , even if vc1 exceeds 14v. if starting the operation with vbulk slow - up is required, adding external components as described bel ow and in fig.7 is recommended. 1) c onnect rsen1 between vc1 and vsense to apply 1.5v or more to vsense terminal, and 2) connect r timer 1 between timer and sgnd to disable f/b loop open protection . please note this circuit is for investi gation only. do not switch on/off the vbulk when using rsen1 as 1) to protect mosfets from undesired heavy switching stress especially in mid - heavy load condition. r t c t c t i m e r c s s 0 . 0 1 u f 1 0 v 1 0 0 0 p c o g / c h 1 % v b u l k 1 0 0 0 0 p f 1 0 v g a t e ( h ) s o u r c e ( h ) g a t e ( l ) s o u r c e ( l ) x u f 1 0 v x u f 1 0 v 1 % 1 % r o c p l r v s e n s e l r v s e n s e h fig.7 additional components
shindengen electric mfg.co.,ltd - 11 - confidential selecting the components of p eripheral circuit 3.1 oscillator ( selecting rt) the timing of gate drive pulse vg(l) and vg(h) is determined by charging and discharging time of timing capacitor ct . vg(l) and vg(h) drive main switches alternately and shoot through current of main switc hes is prohibited by dead time ( dt ) that is equal to discharging time of ct +140ns as shown in fig.8 . the ic adopts non - constant dead time architecture, and the frequency and on - duty varies according to f/b terminal current and frequency increase s respect ively as shown in fig.9 . larger dead time in light load condition secures zvs over a wide frequency range. minimum frequency ( fmin ) is determined by c t and rt . less than 30 0khz for fmax is recommended in continuous operation considering power c onsumptio n. fss depends on ct , for example 185 khz with ct =1000pf typically see characteristic diagram sheet for detail. fig.8 gate drive pulse timing diagram fig.9 frequency/duty vs i(f/b) the value of t entative rt , rt (init) , will be obtained from formula(1) using fmin and ct value . approximate value of fmin will be obtained from formula(2) using actual value of rt . (ct=680pf , rt=18.9kohm) refer to characteristic curves to confirm ct / rt condition. 88 . 1 52 . 2 10 2 . 4 88 . 1 2 1 3 min ) ( ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? t t init t c c f r [ohm] --- (1) ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? t t t t r c r c f / 52 . 2 10 2 . 4 88 . 1 52 . 2 88 . 1 2 1 3 min [hz] --- (2) fig.10 ct / rt internal block 5 v ct rt gnd 2 . 5 v 0 100 200 300 400 500 0 1 2 3 4 5 ifb [ma] f r e q u e n c y [ k h z ] 0 10 20 30 40 50 d u t y [ % ] ct=680pf rt=18.9k ct=820pf rt=16.8k ct=1000pf rt=13.2k ct=1200pf rt=11.6k
shindengen electric mfg.co.,ltd - 12 - confidential vc 1 ct vg ( h ) vsense css 1 . 4 v 13 . 5 v vg ( l ) 0 . 7 v 1 . 1 v fig.11 vsense internal block fig.12 vsense brown out timing diagram 3.2 brown - out protection ( selecting rvsensel ) vsense terminal monitors the input voltag e for halting gate drive pulse and varying the frequency. uvlo function avoids below - resonant state caused by supplying vbulk remaining vc1 is applied, brown - out (quick de crease of input voltage) or black - out (instantaneous interruption). timing diagram of brown - out protection is shown in fig.12. high side resistor of voltage divider is rvsenseh :greater than 3mohm is recommended. required minimum sink current of vsense t erminal is 1ua. low side resistor, rvsensel (init) is obtained from formula( 3 ) and correct value of vbulkreset threshold is obtained from formula( 4 ) by using actual value of rvsensel . this 1.4v threshold is for css resetting without hysterisis,and 1.1v i s for on/off with 0.4v hysterisis.vsense pin can be simply used for on/off function. [ohm] --- (3) [vdc] --- (4) rvsenseh of 3mohm as an example consumes 40mw constantly at ac240v (with out pfc operating ). in the case where pfc convert er with independent ovp function is installed, the voltage divider (associated power consumption) can be eliminated by obtaining vsense voltage from ovp detector of the pfc converter. connect filtering capacitor of around 3.3 - 10n f between vsense terminal a nd gnd. 3.3 soft start ( selecting css) tentative value of soft start timing capacitor css (init) is obtained from approximate formula( 5 ). tss is the time period of which the frequency stabilizes at fmin after vcss reaches around 0.8v . correct value of tss, soft start time period, is obtained from formula( 6 ) using actual value of css. characteristics of css voltage vs operating frequency at css = 4.7uf ( tss = 200ms) is shown in fig.1 3 . 6 ss ss 6 ss ) init ( ss 10 23 c t 10 23 t c ? ? ? ? ? ? ? [f] --- (5) [sec] --- (6) 1.4 r r r v 1.4 - v r 1.4 r vsensel vsensel vsenseh bulkreset bulkreset vsenseh (init) vsensel ? ? ? ? ?
shindengen electric mfg.co.,ltd - 13 - confidential s s tim e vs f re qu e n c y an d te rm in al vo ltag e 0 50 100 150 200 250 0 50 100 150 200 250 time [ms] f s s [ k h z ] 0.0 0.5 1.0 1.5 2.0 s s t e r m i n a l v o l t a g e [ v ] f s s [ k h z] v s s [ v ] ct=1000pf rt=13.2k css=4.7uf fig. 13 . fss characteristics 3.4 over - current protection selecting rocpdet / rocpl o cp(over current protection) operates by detecting positive peak current of resonant tank (drain current of high - side mosfet) beyond the threshold of + 0.34 5 v. the current is detected by sensing resistor rocpdet and its detected voltage is applied to ocp terminal through r/c filter. when the voltage applied to ocp terminal reaches + 0.345 v, timing capacitor ct is charged rapidly and consequently the frequenc y is increased to limit the current / mosfet drain current. t hre s hold level is low enough to minimize ineffective power loss of sensing resistor . filter capacitor is connected between ocp and sgnd to eliminate the influence of parasitic inductance of sensi ng resistor or parasitic inductance. the capacitance value of 1000pf to 10000pf is recommended. fig. 14 . ocp timing diagram
shindengen electric mfg.co.,ltd - 14 - confidential rocpdet is obtained from formula( 7 ) with desired ocp threshold ipk . tentative value of rocpl (init) is obtained from formula( 8 ) and correct value of ipk (th) is calculated from formula( 9 ) using actual value of rocpl . 10 - 47 ohm is recommended as rocph considering ocp terminal sourcing current (180ua typ.) ipk(th) value should be determined carefully to have enough margins in low input voltage / pomax or switching load condition. r o c p l r o c p d e t c r c 1 1 6 1 0 0 0 0 p f fig.15. main resonant current detecting configuration oc p function of mcz5203 activates by detecting positive current (drain current of high - side mosfet) so keep suitable winding direction if half - wave rectification is applied in multiple output converter usage. if ocp acti vates (in the period of high - side driven), succeeding period of low - side driven is limited to 1/ (2 x fmin x 1.8). large negative voltage applied to ocp terminal may cause ocp m a lfunction. if ocp terminal negative voltage is greater than - 0.8v , add 4 0v 1a sbd to clamp the negative voltage. 3. 5 di/dt mode protection mcz5203 adopts pulse by pulse bidirectional didt protection to avoid below resonant mode operation. this function helps to avoid hard switching of main switches in below zvs boundary operation. when ocp terminal voltage ( vocp) exceeds 60mv during the period of ct voltage going bottom to 2.1v ( ct masking period), didt protection is ready to activate. in identical ct saw tooth period , vocp decreasing to 60mv again results in instantaneous c t discharging and gate drive turns off. in negative current direction, threshold voltage is - 60mv. during didt protection is operat ing , c timer is not charged. please note didt threshold is about 1 /6 of ocp threshold. fig. 1 6 . ocp protection fig. 1 7 . di/dt protection ) 9 ( ] a [ 0.345 r r r 10 i ) 8 ( ] ohm [ 0.345 r ipk 10 0.345 r ) 7 ( ] ohm [ ipk 0.345 r det ocp ocpl ocpl ) th ( pk det ocp ) init ( ocpl det ocp ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
shindengen electric mfg.co.,ltd - 15 - confidential 3.6 timer protection selecting c timer ti mer terminal has 2 threshold, 3v and 0.3v. when ocp or f/b loop open protection operates, c timer charging starts and continuous abnormal condition keeps charging c timer with constant 215ua until v(c timer ) reaches 3.0v. once v(c timer ) reached 3v, gate output stops and c timer discharging with constant 10ua sinking starts and continues until v(c timer ) decreases to 0.3v. at the moment v(c timer ) reaches 0.3v, c timer 215ua charging restarts and gate output also restarts with soft starting f unction. timer counter counts the number of times of 3v charging.if count is twice, output will be latched off. when abnormal condition is eliminated and converter enters in normal operation before abnormal 2 counts, c timer is rapidly discharged with 2ma si nking and the counting result is reset. to release latching , restart with supplying vc1 of less than 8v timing chart is shown in fig.18 . 6 10 3 215 ? ? ? ? ttimer ctimer [f] ---- (10) timer burst timing ratio is t timer 1 : tb = 1 : (20+ tss ) , in ca se of c timer =4.7uf / css =2.2uf , t timer =70msec , tb =1.5sec . abnormal signal latch counter prot 3 v refresh ( 1 ) ( 2 ) reset vss 2 . 5 v latch gate out fig.18. timer delay ed burst and latching timing chart
shindengen electric mfg.co.,ltd - 16 - confidential 3.7 high side floating vcc (vb) floa ting high side gate drive voltage source ( vb ) is produced by bootstrapping configuration from stabilized vc 2 10v. 600v soft recovery type ufrd (ultra fast recovery diode) is recommended like d1nk60 (shindengen). vb = vc2 ? vf (dboot) vs terminal is the reference potential for vb , so if negative spike voltage due to turn off current of low side switch and pattern parasitic inductance is too large, vb will be over charged. in case of vb max exceeds 15v , zen er diode clamping is recommended to avoid high side logic malfunction. np mcz dboot cboot 0 . 1 uf 16 v d 1 nk 60 d 1 fk 60 20 15 14 13 21 22 vc 2 pgnd vg ( l ) vb vs vg ( h ) fig. 1 9 . boot strap ping config u ration 3.8 gate driver the gate drivers have 0. 18 a sourc ing and 0. 53 a sink ing current capability at vc2 =10v. typical configurations are show n in fig. 20 a) b). if using small low qg mosfet like 30nc or less, r122/125 and d112/113 will not be required like fig.20 c) due to optimized unbalanced drive capability of mcz5203 . fig. 20 . gate driving config u ration
shindengen electric mfg.co.,ltd - 17 - confidential 4 circuit diagram 4.1 circuit example c 201 r 202 ic 201 t 101 v 1 r 203 r 211 r 210 r 213 c 231 r 231 d 201 9 d 203 vgh vs vb ( nc ) vgl pgnd vc 2 vsen fb ct rt gnd timer ss vc 1 ocp ic 101 c 122 r 110 r 111 c 115 c 114 c 113 r 131 c 112 r 108 pc 101 r 107 r 102 r 101 c 121 c 120 d 110 c 119 r 124 r 126 r 121 r 123 1 4 c 110 q 101 q 102 f 101 c 117 r 112 c 116 cn 102 c 123 c 126 c 111 q 113 gnd vcc vin gnd gnd 7 8 on / off r 103 10 c 205 v 2 d 205 13 d 206 gnd 12 11 c 202 ( nc ) ( nc ) ( nc ) ( nc ) ( nc ) ( nc ) fig. 2 1 . dual output llc
shindengen electric mfg.co.,ltd - 18 - confidential 5 dimensions 5.1 sop22 ( mcz5203 se ) u nits : mm

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